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| R65C51 ASYNCHRONOUS COMMUNICATIONS PRELiMlNARY DESCRIPTION The Rockwell CMOS R65C51 Asynchronous Communications Interface Adapter (ACIA) provides an easily implemented, program controlled interface between 8-bit microprocessor-based systems and serial communication data sets and modems. The ACIA has an internal baud rate generator. This feature eliminates the need for multiple component support circuits, a crystal being the only other part required. The Transmitter baud rate can be selected under program control to be either 1 of 15 different rates from 50 to 19,200 baud, or at l/16 times an external clock rate. The Receiver baud rate may be selected under program control to be either the Transmitter rate, or at l/16 times the external clock rate. The ACIA has programmable word lengths of 5, 6, 7, or 8 bits; even, odd, or no parity; 1, 1'12, or 2 stop bits. The ACIA is designed for maximum programmed the microprocessor (MPU), to simplify hardware tion. Three separate registers permit the MPU to the R65C51's operating modes and' data checking and determine operational status. control from implementaeasily select parameters FEATURES Low power CMOS N-well silicon gate technology Direct replacement for NMOS R6551 ACIA Full duplex operation with buffered receiver and transmitter Data set/modem control functions Internal baud rate generator rates (50 to 19,200) . with 15 programmable bau Program-selectable rate internally or'externally controlled receive . Programmable word lengths, number of stop bits, and pant bit generation and detection Programmable Program reset Program-selectable serial echo mode Two chip selects 1 or 2 MI-Q operation 5.0 Vdc t 5% supply requirements 28-pin plastic or ceramic DIP Full TTL compatibility Compatible processors with. R6500, R6500/' and R65COO microinterrupt control The Command Register controls parity, receiver echo mode, transmitter interrupt control, the state of the RTS line, receiver interrupt control, and the state of the DTR line. The Control Register controls the number of stop bits, word length, receiver clock source, and baud rate. -The Status Register indicates the states of the IRQ, DSR, and DCD lines. Transmitter and Receiver Data Registers, and Overrun, Framing, and Parity Error conditions, The Transmitter and Receiver Data Registers are used for temporary data storage by the ACIA Transmit and Receiver circuits. ORDERING INFORMATION Part No.: R65C51 Temperature Range (TL to TH): Blank = 0% to +70C E= -40% to +85% Frequency Range: 1 = 1 MHz 2 = 2 MHz Package: C = Ceramic P = Plastic Figure 1. R65C51 AClA Pin Configuration Product Description Order No. 2157 Rev. 3, October 1984 Document No. 29651 N60 2-296 RGSCEi'O Asynchronous Communications. Interface Adapter (ACIA) I I . TRANSMIT CONTROL lI t CTS 1 I ; __c > , * __) TxD & TRANSMIT ' DATA REGISTER STATUS REGISTER 4p + > TRANSMIT SHIFT REGISTER Dcd DSR l N RxC ' BAUD -XTLt c RATE GENERATOR __c XTl_O L tDTR ,RTS RECEIVE SHIFT REGISTER a cI a RSl ------ CONTROL REGISTER COMMAND REGISTER ' 1 TIMING 1 t cc $2 RES L RxD * REGISTER I Figure 2. ACIA Internal Organization RECEIVE CONTROL 1 FUNCTIONAL DESCRIPTION : block diagram of the ACIA is presented zy a descrtption of each functional DATA BUS BUFFERS TIMING AND CONTROL The Timing and Control logic controls the timing of data transfers on the internal data bus and the registers, the Data Bus Buffer, and the microprocessor data bus, and the hardware reset features. Timing is controlled by the system 82 clock input. The chip WIII perform data transfers to or from the microcomputer data bus during the $2 high period when selected. All registers will be initialized by the Timing and Control Logic when the Reset (m) line goes low. See the individual register description for the state of the registers following a haraware reset. in Figure 2 followed element of the device. The Data Bus Buffer interfaces the system data lines to the interIal data bus. The Data Bus Buffer is bidirectional. When the %i? line is low and the chip is selected, the Data Bus Buffer .vntes the data from the system data lines to the ACIA internal zata bus. When the Rfi line is high and the chip is selected, :?e Data Bus Buffer drives the data from the internal data bus `3 the system data bus. INTERRUPT LOGIC The Interrupt Logic will cause the IRQ line to the microprocessor `3 50 low when conditions are met that require the attention of :ne mlcroprocessor. The conditions which can cause an inter`uot will set bit 7 and the appropriate bit of bits 3 through 6 in :ne Status Register, if enabled. Bits 5 and 6 correspond to the 3ata Carrier Detect (DCD) logic and the Data Set Ready (DSR) ogle. Bits 3 and 4 correspond to the Receiver Data Register full 3na the Transmitter Data Register empty conditions. These conXons can cause an interrupt request if enabled by the Com-and Register. 110 CONTROL TRANSMllTER AND RECEIVER DATA REGISTERS These registers are used as temporary data storage for the ACIA Transmit and Receive Circuits. Both the Transmitter and Receiver are selected by a Register Select 0 (RSO) and Register Select 1 (RSl) low condition. The Read/Write (R/m) line determines which actually uses the internal data bus: the Transmitter Data Register is write only and the Receiver Data Register 1s read only. Bit 0 is the first bit to be transmitted from the Transmttter Data Register (least significant bit first). The higher order bits follow in order. Unused bits in this register are "don't care". The Receiver Data Regtster holds the first received data bit In bit 0 (least significant bit first). Unused high-order bits are "0". Parity bits are not contained in the Receiver Data Register. They are stripped off after being used for parity checking. The IO Control Logic controls the selectlon of internal registers `n Preparation for a data transfer on the Internal data bus and !he direction of the transfer to or from the register. The registers are selected by the Receiver Select (RSl, RSO) and Read Write (R/w) lines as described later in Table 1. 2-297 R&C51 STATUS REGISTER Asynchronous Communications Interface Adapter (ACIA Parity Error (Bit 0), Framing Error (Bit l), and Overrun (2) None of these bits causes a processor interrupt to occur, t they are normally checked at the time the Receiver Data Re ister is read so that the validity of the data can be verified. The bits are self clearing (i.e., they are automatically cleared at: a read of the Receiver Data Register). The Status Register indicates the state of interrupt conditions and other non-interrupt status lines. The interrupt conditions are the Data Set Ready, Data Carrier Detect, Transmitter Data Register Empty and Receiver Data Register Full as reported in bits 6 through 3, respectively. If any of these bits are set, the Interrupt (IRQ) indicator (bit 7) is also set. Overrun, Framing Error, and Parity Enor are also reported (bits 2 through 0 respectively). 7 t 6 5 4 3 2 1 0 , Receiver Data Register Full (Bit 3) This bit goes to a 1 when the ACIA transfers data from :' Receiver Shift Register to the Receiver Data Register. and go. to a 0 (is cleared) when the processor reads the Receiver D; Register. IRG DSR DCD TDRE RDRE OVRN FE PE 4 Bit 7 0 1 Bit 6 0 1 Bit 5 0 1 Bit 4 0 1 Bit 3 0 1 Bit 2 0 1 Bit 1 0 1 Bit 0 0 1 Interrupt (IRQ) No interrupt Interrupt has occurred Data Set Ready (DSR) DSR low (ready) DSR high (not ready) Transmitter Data Register Empty (Bit 4) Data Carrier Detect (DCD) DCD low (detected) DCD high (not detected) Transmitter Not empty Empty Receiver Data Register Full Not full Full Overrun* No overrun Overrun has occurred Framing Error' No framing error Framing error detected Parity Error* No parity error Parity error detected Data Register Empty This bit goes to a 1 when the ACIA transfers data from tr Transmitter Data Register to the Transmitter Shift Register, ar goes to a 0 (is cleared) when the processor writes new daonto the Transmitter Data Register. Data Carrier Detect (Bit 5) and Data Set Ready (Bit 6) These bits reflect the levels of the DCD and DSR inputs to tt ACIA. A 0 indicates a low level (true condition) and a 1 indicate a high level (false). Whenever either of these inputs chant state, an immediate processor interrupt (IRQ) occurs. unless : 1 of the Command Register (IRD) is set to a 1 to disable IR( When the interrupt occurs, the status bits indicate the levels the inputs immediately after the change of state occurred. SL sequent level changes will not affect the status bits until t' Status Register is interrogated by the processor. At that tirr another interrupt will immediately occur and !he status !I reflect the new input levels. These bits are not automatica cleared (or reset) by an internal operation. Interrupt (Bit 7) `No interrupt occurs for these conditions Reset initialization 76543210 0 -1-I 1 0 0 0 This bit goes to a 1 whenever an interrupt condition occurs ar goes to a 0 (is cleared) when the Status Register IS read. - -/-(- 1 - 0- 0 Hardware reset _ ' Program reset 2-298 R65C5 1 CONTROL REGISTER Y -. 7 c WL m Asynchronous Communications Interface Adapter (ACIA) Selected Baud Rate (Bits 0, 1, 2, 3) These bits select the Transmitter baud rate, which can be at `I16 an external clock rate or one of 15 other rates controlled by the internal baud rate generator. If the Receiver clock uses the same baud rate as the transmitter, then RxC becomes an output and can be used to slave other circuits to the ACIA. Figure 3 shows the Transmitter and Receiver layout. antrot Register selects the desired baud rate, frequency word length, and the number of stop bits. 6 5 4 3 2 S8R 1 0 . SBN ' Bit 7 ? i . . : WLl 1 RCS SBR3 SBR2 SBRl SBRO WLO \ Stop Bit Number (SBN) 1 Stop bit 2 Stop bits I 1:~Stop bits For WL = 5 and no parity 1 Stop bit For WL = 8 and parity Word Length No. Bits 8 7 6 5 I 1 RECEIVER I-_r SHIFT REGISTER J t RxD Bits 6-5 _ `3 3 3 . . r (WL) * . -? 1 0 CLOCK DIVIDER e (16) 4 SYNC LOGIC ` RxC 1 Bit 4 0 1 Receiver Clock Source External receiver clock Baud rate (RCS) XTU C XTLOC . BAUD RATE + GENERATOR f t t t, BIT 4 CLOCK DIVIDER (16) Bits 3-o 3 2 -Ti0 0 0 0 0 0 0 3 1 0 1 0 0 9 : 1 1 7 1 0 0 0 0 1 ? 1 1 1 1 1 1 Selected Baud Rate (SBR) 1 0 Baud 0 016x 0 1 50 1 0 75 1 1 109.92 0 0 134.58 0 1 150 1 0 300 1 1 600 0 0 1200 0 1 1800 1 0 2400 1 1 3600 0 0 4800 0 1 7200 1 0 9600 1 1 19.200 r;;T;;:" REGISTER 1 TRANSMITTER 1 SHIFT REGISTER I-- TxD Figure 3. Transmitter/Receiver Clock Circuits Receiver Clock Source (Bit 4) This bit controls the clock source to the Receiver. A 0 causes the Receiver to operate at a baud rate of l/16 an external clock. A 1 causes the Receiver to operate at the same baud rate as is selected for the transmitter. Word Length (Bits 5, 6) ?eset Initialization 76543210 oooo000 `ZJZFQ$j These bits determine the word length to be used (5, 6, 7 or 8 bits). 0 Hardware reset (i%%) Program reset Stop Bit Number (Bit 7) This bit determines the number of stop bits used. A 0 always indicates one stop bit. A 1 indicates 1% stop bits if the word length is 5 with no parity selected, 1 stop bit if the word length is 8 with parity selected, and 2 stop bits in all other configurations. 2-299 R65C51 COMMAND REGISTER Asynchronous Communications Interface Adapter (ACIA Data Terminal Ready (Bit 0) This bit enables all selected interrupts and controls the state o* the Data Terminal Ready (m) line. A 0 indicates the microcomputer system is not ready by setting the DTR line high. b 1 indicates the microcomputer system is ready by setting the DTR line low. fi line low. m also enables and disables the transmitter and receiver. Receiver Interrupt Control The Command Register controls specific modes and functions. 76543210 TIC - IRD DTR PME REM 1 TIC1 TIC0 PNCl PNCO PMC Bits 7-6 7 6 `i;j- 0 0 1 1 0 1 1 Parity Mode Control (PMC) Odd parity transmitted/received Even parity transmitted/received Mark parity bit transmitted Parity check disabled Space parity bit transmitted Parity check disabled Parity Mode Enabled (PME) Parity mode disabled No parity bit generated Parity check disabled . Parity mode enabled Receiver Echo Mode (REM) Receiver normal mode Receiver echo mode bits 2 and 3 Must be zero for receiver echo mode, m be low. Transmitter RTS RTS RTS I?% = = = = Interrupt Control (TIC) (Bit 1) This bit disables the Receiver from generating an interrupt whee set to a 1. The Receiver interrupt is enabled when this bit is SE to a 0 and Bit 0 is set to a 1. Transmitter Interrupt Control (Bits 2, 3) line an' These bits control the state of the Ready to Send (m) the Transmitter interrupt. Bit 5 0 Receiver Echo Mode (Bit 4) A 1 enables the Receiver Echo Mode and a 0 disables the Receiver Echo Mode. When bit 4 is a 1 bits 2 and 3 must be 0. In the Receiver Echo Mode, the Transmitter returns eact transmission received by the Receiver delayed by one-half bitime. will 1 Bit 4 0 1 Parity Mode Enable (Bit 5) This bit enables parity bit generation and checking. A 0 disable: parity bit generation by the Transmitter and parity bit checking by the Receiver. A 1 bit enables generation and checking c parity bits. Bits 3-2 3 2 00 0 1 1 0 1 1 High, transmitter disabled Low, transmit interrupt enabled Low, transmit interrupt disabled Low, transmit interrupt disabled transmit break on TxD Parity Mode Control (Bits 6, 7) These bits determine the type of parity generated by the Trans mitter, (even, odd, mark or space) and the type of parity chec done by the Receiver (even. odd, or no check). Reset Initialization 76543210 I ~olololo~o~o~o~o~ 1. --1-1-t ]ojo~O~O~o, Hardware reset (m) Program reset Bit 1 0 1 Bit 0 0 1 Receiver Interrupt Request Disabled (IRD) IRQ enabled (receiver) IRQ disabled (receiver) Data Terminal Ready (DTR) Data terminal Data terminal not ready (m high)' ready (fi low) NOTE `The transmitter is disabled immediately. The receiver is disabled but will first complete receiving a byte in process of being received. 2-300 5s Asynchronous Communications Interface Adapter (ACIA) NTERFACE SIGNALS the ACIA interface signals associated with the and the modem. 1 Interrupt Request (m) The iis1s pin is an interrupt output from the interrupt control logic. It is an open drain output, permitting several devices to be connected to the common m microprocessor input. Normally a high level, m goes low when an interrupt occurs. _ *e-a srows 2. -&zrocessor a--m Data Bus (00-07) The eight data line (DO-D7) pins transfer data between the processor and the ACIA. These lines are bi-directional and are normally high-impedance except during Read cycles when the ACIA is selected. cl I/O CONTROL 62 RES TRANSMIT DATA & SHIFT REGISTERS -_) TxD c-OCD .--iz% Chip Selects (CSO, a) RxC XTLI XTLO The two chip select inputs are normally connected to the processor address lines either directly or through decoders. The ACIA is selected when CSO is high and C%i is low. When the ACIA is selected, the internal registers are addressed in accordance with the register select lines (RSO, RSl). BAUD RATE GENERATOR W * --c I COMMAND REGISTER I Register Selects (RSO, RSl) The two register select lines are normally connected to the processor address lines to allow the processor to select the various ACIA internal registers. Table 1 shows the internal register select coding. C Rx0 Figure 4. ACIA Interface Diagram Table 1. ACIA Register Selection Register Operation RSl RSO L ICROPROCESSOR eset (RES) INTERFACE L Rl%ij=Low Write Transmit Data Resister Programmed Reset Rm = High Read Recewer Data Reaister mng system initialization a low on the RES input causes a irdware reset to occur. Upon reset, the Command Register Id the Control Register are cleared (all bits set to 0). The atus Register is cleared with the exception of the indications Data Set Ready and Data Carrier Detect, which are externally )ntrolled by the DSR and DCD lines, and the transmitter Empty :. which is set. RES must be held low for one 82 clock cycle r a reset to occur. l-l H Write Control Register Read Control Register I Iput Clock (82) ie input clock is the system 82 clock and clocks all data trans! `ers between the system microprocessor and the ACIA. i Read/Write (RN) Only the Command and Control registers can both be read and written. The programmed Reset operation does not cause any data transfer, but is used to clear bits 4 through 0 in the Command register and bit 2 in the Status Register. The Control Register is unchanged by a programmed Reset. It should be noted that the programmed Reset is slightly different from the hardware Reset (m); refer to the register description. 1 The R/W input. generated by the microprocessor controls the i direction of data transfers. A high on the FUfi pin allows the i Xocessor to read the data supplied by the ACIA, a low allows i a write to the ACIA. 2-301 R65C51 ACIA/MODEM INTERFACE Asynchronous Communications Interface Adapter (ACIA Clear to Send (m) The Cm input pin controls the transmitter operation. The enabl state is with CTS low. The transmitter is automatically disable if CTS is high. Crystal Pins (XTLI, XTLO) These pins are normally directly connected to the parallel mode external crystal (1.8432 MHz) to derive the various baud rates. Alternatively, an externally generated clock can drive the XTLI pin, in which case the XTLO pin must float. XTLI is the input pin for the transmit clock. Data Terminal Ready (m) This output pin indicates the status of the ACIA to the moderr A low on DTR indicates the ACIA is enabled, a high indicate: it is disabled. The processor controls this pin via bit 0 of the Command Register. Data Set Ready (m) Transmit Data (TxD) The TxD output line transfers serial nonreturn-to-zero (NRZ) data to the modem. The least significant bit (LSB) of the Transmit Data Register is the first data bit transmitted and the rate of data transmission is determined by the baud rate selected or under control of an external clock. This selection is made by programming the Control Register. The m input pin indicates to the ACIA the status of the modem. A low indicates the "ready" state and a high, "not. ready. " Receive Data (RxD) The RxD input line transfers serial NRZ data into the ACIA from `the modem, LSB first. The receiver data rate is either the programmed baud rate or under the control of an externally generated receiver clock. The selection is made by programming the Control Register. Data Carrier Detect (DCb) The m input pin indicates to the ACIA the status of the carrierdetect output of the modem. A low indicates that the modem carrier signal is present and a high, that it is not. TRANSMITTER Continuous AND RECEIVER OPERATION Data Transmit Receive Clock (RxC) The RxC is a bi-directional pin which is either the receiver 16x clock input or the receiver 16x clock output. The latter mode results if the internal baud rate generator is selected for receiver data clocking. Request to Send (m) In the normal operating mode, the interrupt request output (m) signals when the ACIA is ready to accept the next data word to be transmitted. This interrupt occurs at the beginning of the Start Bit. When the processor reads the Status Register of the ACIA, the interrupt is cleared. The processor must then identify that the Transmit Data Register is ready to be loaded and must then load it with the next data word. This must occur before the end of the Stop Bit, otherwise a continuous "MARK" will be transmitted. Figure 5 shows the continuous Data Transmit timing relationship. The m output pin controls the modem from the processor. The state of the RTS pin is determined by the contents of the Command Register. CHAR=n CHAR=n+l CHAR =n+2 CHAR =cn+3 PROCESSOR INTERRUPT (TRANSMIT REGISTER / PROCESSOR.REAOSSTATUS OATA EMPTY) REGISTER, TO CLEAR CAUSES IRO \ \ PROCESSOR MUST LOAONEWOATA IN THIS TIME INTERVAL; CONTINUOUS OTHERWISE, "MARK" IS TRANSMITTED Figure 5. Continuous Data Transmit 2-302 Asynchronous Communications Interface Adapter (ACIA) --- continuous Data Receive OVerWI 5,mliar to the Continuous Data Trasit case, the normal Jperatlon of this mode is to assert IRQ when the ACIA has --led a full data word. This occurs at about `116 point through :m Stop Bit. The processor must read the Status Register and read the data word before the next interrupt, otherwise the condition occurs. Figure 6 shows the continuous Data Receive Timing Relationship, CHAR # n CHAR *II*1 CHAR Sn+2 Cn*Rpn+3 1 PROCISSOR INtERRUrT ABOUT 0110 OCCURS/ INTO / \ \ PROCESSOR RECEIVER TIME OVERRUN MUST READ DATA IN THIS OTblERWISE. OCCURS I \ PROCPSIOR REGISTER. TO CLEAR READS CAUSES STATUS %8 LAST STOP SIT. PARITY. OVERRUN. AND FRAMING ERROR ALSO, UPOATED \ INTERVAL; Figure Continuous Data Receive 6. Transmit Data Register Not Loaded by Processor If the processor is unable to load the Transmit Data Register in the allocated time, then the TxD line goes to the "MARK" condition until the data is loaded. IRQ interrupts continue to occur at the same rate as previously, except no data is transmitted. When the processor finally loads new data, a Start Bit immediateiy occurs, the data word transmission is started, and another interrupt is initiated, signaling for the next data word. Figure 7 shows the timing relationship for this mode of operation. CHAR#n CONTINUOUS "MARK" CHAR 5tn+l CklAR =n+2 TX0 FJz- ,m, _ CHARACTER TIME -_ I ,mqq$5f s:art So 8, IRa Iu / , Ill I PROCESSOR INTERRUPT FOR DATA ' ,&j REGISTER EMPTY PROCESSOR READS STATUS REGISTER I NO DATA IS TRANSMITTEO NEW DATA, IMMEDIATELY TRANShllSSION STARTS AND INTERRUPT OCCURS, INDICATING TRANSMIT DATA REGISTER EMPTY Flgure 7. Transmit DataRegister Loaded Processor Not by 2-303 R65C5 1 Effect of CTS on Transmitter Asynchronous Communications Interface Adapter @CIA) ?f% is the Clear-to-Send normally low (true modem problems. MARK" condition nd stop bit) have signal generated by the modem. It is state) but may go high in the event of some When this occurs, the TxD line goes to the after the entire last character (including parity been transmitted. Bit 4 in the Status Register tn CHAR=n+l indicates that the Transmitter Data Register is not empty and i% is not asserted. CTS is a transmit control line only, and has no effect on the ACIA Receiver Operation. Figure 8 shows the timing relationship for this mode of operation. CHAR CONTINUOUS "MARK" TX0 IRQ I CLEAR-TO-SEND I n-l NOT t CLEAR-TO-SEND m IS NOT ASSERTED AGAIN UNTIL m GOES `Ow f Ffs GOES HIGH. INDICATING MODEM IS NOT READY TO RE?%ibE DATA. TxO GOES TO "MARK" CONDITION AFTER COMPLETE CHARACTER IS TRANSMITTED. Figure 8. c Effect of Overrun on Receiver Effect of CTS on Transmitter lf the processor does not read the Receiver data Register in the ; allocated time, then, when the following interrupt occurs, the ' new data word is not transferred to the Receiver Data Register, but the Overrun status bit is set. Thus, the Data Register will contain the last valid data word received and all following data is lost. Figure 9 shows the timing relationship for this mode. CHAR=n CHARfin+ CHAR =n+2 CHAR In+3 Rx0 ~,~~,~I~lr~ PROCESSOR INTERRUPT FOR RECEIVER DATA FULL REGISTER \ PROCESSOR RECEIVER DATA REGISTER NOT UPDATED. BECAUSE PROCESSOR DID NOT READ PREVIOUS DATA, IN STATUS OVERRUN BIT SET REGISTER I REGISTER OVERRUN STATUS StT SET IN REGISTER Figure 9. Effect of Overrun on Receiver RfjSCS f Ecno Mode -. Asynchronous Communications Interface Adapter (ACIA) Timing p 2_w a,!oce.the TxD line re-transmits the data on the RxD xoaved by `? of the bit time, as shown in Figure 10. 112 DATA BIT DELAY Figure 10. Echo Mode Timing Effect of CTS on Echo Mode Operation the Receiver Data Register is full in response to an R, so the processor has no way of knowing that the Transmitter has ceased to echo. See Figure 11 for the timing relationship of this mode. `n Echo Mode, the Receiver operation is unaffected by m, qowever. the Transmitter is affected when CTS goes high, i.e., :he TxD line immediately goes to a continuous "MARK" con31t!on. In this case, however, the Status Request indicates that CHAR#tn CHAR#n+l CHARtin+ CHARtin+ Rx0 $`l~~l:_I~,~,~ I I I 1 III J I III t I `I I III t NOTCLEAR-TO-SENO I CONTINUOUS "MARK" I UNTIL Ffs I I I GOES I 1 I LOW , \ / 1 TxO p Ist&=tl S,, 1 S, 1 1 `N 1 P r . . .. 3 GOES TO CONDITION "FALSE" NORMAL RECEIVER REGISTER INTERRUPTS DATA FULL - Figure 11. Effect of CTS on Echo Mode 2-305 a R65CSl Overrun in Echo Mode If Overrun occurs in Echo Mode, the Receiver is affected the same way as a normal overrun in Receive Mode. For the retransmitted data, when overrun occurs, the TxD line goes to the "MARK" condition until the first Start Bit after the Receiver Dar Register is read by the processor. Figure 12 shows the timir relationship for this mode. Asynchronous Communications Interface Adapter (ACM IRQ \ t /i )I 1 \ nJ DATA A b 1 RI t TxO DATA RESUMES PROCESSOR INTERRuFT FOR RECEIVER OATA REGISTER PROCESSOR FINALLY READS RECEIVER REGISTER. (=nb REAO RECEIVER LAST VALIO CHARACTER PROCESSOR REAOS STATUS REGISTER OVERRUNOCCURS TxO GOES "MARK" CONDITION To PROCESSOR INTERRUPT FOR CHAR *JI IN RECEIVER DATA REGISTER Figure 12. Overrun in Echo Mode Framing Error Framing received 4 in the Register to m, Error is caused by the absence of Stop Bit(s) on data. A Framing Error is indicated by the setting of bit Status Register at the same time the Receiver Data Full bit is set, also in the Status Register. In response generated by RDRF, the Status Register can also be checked for the Framing Error. Subsequent data words a tested for Framing Error separately, so the status bit will alwa reflect the last data word received. See Figure 13 for Framl Error timing relationship. RX0 (EXPECTED) RR0 (ACTUAL) NOTES: 1. FRAMING INHISIT ERROR RECEIVER DATA DOES NOT OPERATION. IS OK. cl MISSING STOP SIT / I PROCESSOR INTERRUPT, FRAMING ERROR BIT SET 2. IF NEXT FRAMING WORD ERROR IS CLEARED. Figure 13. Framing Error fq6sCSf gmt of J i Asynchronous Communications Interface Adapter (ACIA) on Receiver output Indicating the status of the carrier-freclrcult of the modem. This line goes high for :z -ccem _;s;ec:.on -arr:er. Normally, when this occurs, the modem will I .- c:ng data some time later. The ACIA asserts IRQ 72 changes state and indicates this condition via _ *he Status Register. -.Js -9. , I=Q :! s L.5, -be? Once such a change of state occurs, subsequent transitions will not cause interrupts or changes in the Status Register until the first intermpt is serviced. When the Status Register is read by the processor, the ACIA automatically checks the level of the DCD line, and if it has changed, another ii% occurs (see Figure 14). CONTINUOUS `MARK" x 1 t NORMAL PROCESSOR INTSRRupT PROCESSOR INTERRUPT FOR GOING m HIGH ' III--T-t AS LONG AS cicD IS HIGH. NO FURTHER INTERRUPTS FOR WILL RECEIVER OCCUR PROCESSOR INTERRUPT FOR GOING DC0 LOW NO INTERRUPT WILL HERE. OCCUR SINCE PROCESSOR INTERRUPT FOR RECEIVER DATA RECEIVER IS NOT ENAELEO UNTIL FIRST START BIT DETECTED Figure 14. Effect of DCD on Receiver iming with 1% Stop Bits trailing half-Stop Bit. Figure 15 shows the timing relationship for this mode. `s possible to select 1% Stop Bits, but this occurs only for .Dlt data words with no parity bit. In this case, the IRQ asserted r Receiver Data Register Full occurs halfway through the CHARtin CHARC~+I 1x1 m-1 m-L t PROCESSOR INTERRUPT OCCURS HALFWAY THROUGHT THE 112 STOP BIT Figure 15. Timing with 1 l/z Stop Bits 2-307 R65C51 Transmit Continuous "BREAK" Asynchronous Communications Interface Adapter (ACIA) Note If, while operating in the Transmit Continuous "BREAK" mode, the CTS should go to a high, the TxD will be overridden by the m and will go to continuous "MARK" at the beginning of the next character transmitted after the CTS goes high. This mode is selected via the ACIA Command Register and causes the Transmitter to send continuous "BREAK" characters, beginning with the next character transmitted. At least one full "BREAK" character will be transmitted, even if the processor quickly re-programs the Command Register transmit mode. Later, when the Command Register is programmed back to normal transmit mode, an immediate Stop Bit will be generated and transmission will resume. Figure 16 shows the timing relationship for this mode. NORMAL INTERRUPT I PERIOD WHICH - DURING PROCESSOR POINT MODE AT wnlcn `PROCESSOR' INTERRUPT TO LOAD TRANSMIT DATA SELECTS CONTINUOUS "BREAK" PROCESSOR SELECTS NORMAL TRANSMIT MOGE Figure 16. Receive Continuous "BREAK" Transmit Continuous "BREAK" In the event the modem transmits continuous "BREAK" characters, the ACIA will terminate receiving. Reception will resume only after a Stop Bit is encountered by the ACIA. Figure 17 shows the characters. timing relationship for continuous "BREAt -_ RX0 rl Sl -_ CONTINUOUS \ "BREAK" I lsNl p lst~pli,, I 1 PROCESSOR INTERRUPT FOR RECEIVER DATA REGISTER FULL I PROCESSOR BREAK EVEN GIVE AU A AND PARITY ZEROS INTERRUPT FRAMING CHECK I /m-NO--j MORE INTERRUPTS SET. \NOlNTERRUPT SINCE RECEIVER DISABLE0 UNTIL FIRST STOP BIT I NORMAL RECEIVER INTERFltJPl WITH ALSO BREAK) ERROR WILL PARITYERROR EVEN BECAUSE (CONTINUOUS PARITY. REPRESENT Figure 17. Receive Continuous "BREAK" a Asynchronous Communications Interface Adapter (ACIA) ~ATUS REGISTER OPERATION MISCELLANEOUS 1. If Echo Mode is selected, %!? goes low. 2. If Bit 0 of Command *-_2 Z' r-0 soecial funCtiOnS of the various status bits, there 5 3 st;Sej:eo sequence for checking them. When an interrupt Lz_`s. :"1 XIA should be interrogated, as follows: Register (m) is 0 (disabled), then: za;c _.. -' 5:&d `s Register Subsequent -- 3 ,-:era!:on automatically clears Bit 7 (m). ..lrs: crs cn DSR and DCD will cause another interrupt. sycK m (Bit 7) in the data read from the Status Register a) All interrupts are disabled, including those caused by DCD and DSR transitions. b) Transmitter is disabled immediately. c) Receiver is disabled. but a character currently being received will be completed first. 3. Odd parity occurs when the sum of all the 1 bit? in the data word (including the parity bit) is odd. . not sel. :he interrupt source is not the ACIA. 4. In the receive mode, the received parity bit does not go into :?eCK =c3 and DSR the Receiver Data Register, but generates parity error or no parity error for the Status Register. 5. Transmitter These must be compared to their previous levels, which must lave oeen saved by the processor. If they are both 0 (modem on-line I and they are unchanged then the remaining bits qust be cnecked. Cfieck RDRF (Bit 3) Check ior Receiver Data Register Full. Check Parity, Overrun, and Framing Error (Bits O-2) if the Receiver Data Register is full. Check TDRE (Bit 4) and Receiver may be in full operation simultaneously. This is "full-duplex" mode. 6. If the RxD line inadvertently goes low and then high right after a Stop Bit, the ACIA does not interpret this as a Start Bit, but samples the line again halfway into the bit to determine if it is a true Start Bit or a false one. For false Start Bit detection, the ACIA does not begin to receive data, instead, only a true Start Bit initiates receiver operation. 7. Precautions to consider with the crystal oscillator circuit: ChecK ior Transmitter Data Register Empty. exist, then 5 must have If none of the above conditions gone to the false (high) state. a) The external crystal should be a "series" mode crystal. b) The XTALI input may be used as an external clock input. The unused pin (EXTALO) must be floating and may not be used for any other function. 8. m PROGRAM RESET OPERATION A program reset occurs when the processor performs a write speration ro the ACIA with RSO low and RSl high. The program `eset operates somewhat different from the hardware reset $RES pin) and is described as follows: and DSR transitions, although causing immediate processor interrupts, have no affect on transmitter operation. Data will continue to be sent, unless the processor forces transmitter to turn off. Since these are high-impedance inputs. they must not be permitted to float (un-connected). If unused, they must be terminated either to GND or Vcc. GENERATION Divisors OF NON-STANDARD BAUD RATES 1. Internal formats registers are not completely cleared. Check register for the effect of a program reset on internal registers. The internal counter/divider circuit selects the appropriate divisor for the crystal frequency by means of bits O-3 of the AClA Control Register, as shown in Table 2. 2. The DTR line goes high immediately. 3. Receiver and transmitter interrupts are disabled immediately. If IRQ ;s low when the reset occurs. rt stays low until serviced. unless interrupt was caused by DCD or DSR transition. 4. DCD and DSR interrupts are disabled immediately. If IRQ is -low and was caused by DCD or DSR. then it goes high, also DCD and DSR status bits subsequently lines. although no interrupt will occur. will follow the input Generating Other Baud Rates By using a different crystal, other baud rates mav be generated. These can be determined by: Crystal Frequency Baud Rate = Divisor Furthermore. it is possible to drive the ACIA with an offchIP oscillator to achieve other baud rates. In this case, XTALI (pin 6) must be the clock input and XTALO (pin 7) must be a noconnect. 5. Overrun cleared. If set. R65C51- Asynchronous Communications Interface Adapter (ACIA) Table 2 Control Regieter Bite 3 2 1 0 Divisor Selection Baud Rete Genereted With 1.6432 Mljz Crtstrl Baud Rete Generated with a crystal of Frequency (F) Dlviaor Selected For The Internel Counter 0 I / 0 0 0 0 0 0 1 I I I No Divisor Selected I I 16 x External Clock at Pin RxC -. ..1.6432 x lad = 50 16 x External Clock I at Pin RxC F 36,864 F 36.064 36,864 1.8432 x 106 0 0 1 0 24,576 I i 24.576 1.8432 x 16 = 75 1 = 109.92 24,576 F I 1I I 0 0 0 0 1 1 1 I I I 16,769 1.8432 x 106 = 134.51 13.704 1.8432 x 10 I 16,769 F 13,704 F II k I [ [ 1 t 1 f I i 0 0 13,704 1 0 1 12,288 12,288 1.8432 x l@ = 150 12,280 F f 300 6,144 F = 600 3,072 F = 1,200 1,536 F = 1,800 0 1 1 0 6,144 6,144 1.8432 x 108 0 1 1 1 3,072 3,072 1.8432 x 106 10 0 0 1,536 1,536 1.6432 x 16 L i I I 1,024 1.8432 x lO* = 2.400 768 1.8432 x 10' I 1.024 F II tIlOl1 i I 1 l0l0 766 1 1 I 512 I I I I I I = 3,600 , = 4,800 768 F 512 1.8432 x 106 384 1.8432 x 108 512 F 384 F 1 1 0 1 256 1.8432 x 106 256 = 7,200 256 F = 9,600 192 F = 19,200 I 96 ! D i E 1 1 1 0 192 192 1.8432 x loa 11 1 1 1 1 1 96 96 1 1 Asynchronous Communications Interface Adapter (ACIA) &@,osflC LOOP-BACK ii g-3 i) $.mil _~ :-ec = OPERATING MODES an ACIA loop-back operation. In this way, the processor can easily perform local loop-back diagnostic testing. Remote loop-back does not require this circuitry, so LLB must be set low. However, the processor must select the following: Control Register bit 4 must be 1, so that the transmitter clock equals the receiver clock. Command Register bit 4 must be 1 to select Echo Mode. c Command Register bits 3 and 2 must be 1 and 0, respectively to disable IRQ interrupt to transmitter. Command Register bit 1 must be 0 to disable IRQ interrupt for receiver. In this way, the system re-transmits received data without any effect on the local system. , L , XK diagram for a system incorporating ? =$Lre 18. x cesiraole to include in the system a facility for "loop.ss;,rg. =f which there are two kinds: ,=s-Back In this disconits own checks _-1. : _-~_~acK Yom the point of view of the processor. _le :r,e ,Modem and Data Link must be effectively --L::ec ?,?a :he ACIA transmitter connected back to .yYtr~r ~3 fhat the processor can perform diagnostic -- :l.e system. excluding the actual data channel. ioop-Back `. +To:e ,203-DaCK !rom the point of view of the Data Link and ' ' In rhis case, the processor, itself, is disconnected gc al received data is immediately Tetransmitted, so the sys;em on rhe other end of the Data Link may operate indexendent of !he local system. t.@cem. !"?.e XIA does not contain automatic loop-back operating ;-zces. 3ut they may be implemented with the addition of a ji,-a:l amount of external circuitry. Figure 19 indicates the necj!ssarl; logic to be used with the ACIA. The LLB line is the pos5.ve-true signal to enable local loop-back operation. Essentially, :* `__3 = nigh does the following: `Disables 1. Disables !. Connects MICROPROCESSOR v outputs TxD, fi, inputs and RTS (to Modem). CTS, DSR (from Modem). to respective RxD, z, II.e.. L :- transmitter outputs TxD to RxD, DTR to m, receiver inputs w Figure 18. A6551 _-__ ATS to m). I/O MODEM r-l I I 4 TO DATA LINK LB may be tied to a peripheral control pin (from an R65C21 i ;: r R65C24. for example) to provide processor control of local f_ I j Simplified System Diagram I I I -- --Rx0 DC0 CTS DSR *SEL I, 1: +5 i STB 74157 MODEM TxD DTR RfS 1 1Y 2Y 3Y 4Y - NOTES: 1. HIGH ON LLB SELECTS LOCAL LOOP-BACK MODE. 2. HIGH ON 74157 SELECT INPUT GATES "B" INPUTS - 1 48 4A- TO "Y" OUTPUTS; LOW GATES "A" TO "Y". I Figure 19. Loop-Back Circuit Schematic 3_111 R65C51 READ TIMING DIAGRAM Asynchronous Communications Interface Adapter (AC kzCY tCH __i r ,c- I Timing diagrams for transmit with external clock, receive with external clock, and m generation are shown in Figures 20, 21 and 22, respectively. The corresponding timing characteristics are listed in Table 3. Table 3. Transmit/Receive Characteristics XTLI (TRANSMIT CLOCK INPUT) Ij---i tCL-- tDD TxD `KNOTE: TxD RATE IS 1116 TxC RATE Figure 20. Transmit Timing with External Clock Transmit/Receive Clock High Time Transmit/ Receive Clock Low Time XTLI to TxD Propagation Delay RTS Propagation fcli tCL 175 175 500 175 175 - 500 ns ns ns ns ns RxC (INPUT) kCY - -.tcH --a t0D - l fmy I - l tlR0 - 500 I 500 - I 500 I 500 1 IF--- tcL--- Delay IRQ Propagation Delay (Clear) Notes: [tR. tF = 10 to 30 ns) 1 `The baud rate with external clocking is: NOTE: Rx0 RATE IS 1116 RxC RATE Figure 21. Receive External Clock Timing B&d Rate = 16 x tccv *tlRQ' IRQ (CLEAR) Figure 22. Interrupt and Output Timing f irr;sCSl CHARACTERISTICS Asynchronous 1 MHz parameter Symbol . bYC 2 MHz Max - Mln 1000 400 120 0 120 0 120 20 Min 500 200 Max Unit ns ns 22 :,c:e :2 -`,.se Yme .Vldth Set-Up tc Time tACW bAl+ a:,~ :c:.5~s - 60 0 60 0 60 - ns ns nS nS Aold Time Time Time a*,? +I-tip = a.5 -Oq ~3~3 twcw kwn tclcw 4+W 3~s Set-Up Time 3~s ns 100 ns llS flS zala aeac leaa BUS Hold Time Time (Valid Data) Time Time (Invalid Data) 200 - 10 10 20 Access ' km b!R (CDA 20 40 rold %rfve ns Notes: * v-z = 5.ov iwo. 2. T, = T, to T,. 3. t= ana tr = 10 to 30 ns. #- VIH CSO,B,, RSo, AS, VIH VIL I / tDCW _!_--t- tHW--.+i VIL DATA BUS VIH VIL Figure 23. Write Timing Diagram /I I--WCR- It---- tCQR-' I "IL DATA BUS Figure 24. Read Timing Characteristics 2-313 r f " q i; R65C51 ABSOLUTE MAXIMUM Asynchronous Communications Interface Adapter (ACIA RATINGS' `NOTE: Stresses above those listed may cause permaner damage to the device. This is a stress rating only and functionc operation of the device at these or any other conditions abov those indicated in other sections of this document is not implies Exposure to absolute maximum rating conditions for extende periods may affect device reliability. OPERATING CONDITIONS DC CHARACTERISTICS (Vcc = 5.OV f5%, I I j Input High Voltage : Input Low Voltage ! Input Leakage Current: I 02, Rm. !?i%. CSO. a, : RSO, RSI. i5fs, RxD, bFB, DSR ITSI - Vss = 0, TA = TL to T", unless otherwise noted) Parameter Symbol VIH VI, IIN Mln 2.0 -0.3 TYP fl it2 - Max Vcc +0.8 f2.5 f10 - Unit V V fi lLA V Test Conditlons v,, = ov to vcc V,, = 5.25V V,, = 0.4V to 2.4V V,, = 5.25V v,, = 4.75v Input Leakage Current (Three State Off) DO-07 -DO-07, TxD. RxC. RTS. DTR m. TBd j Output High Voltage: Von 2.4 1 ILOAD= -loo d 1 Output Low Voltage: 00-07. TxD. RxC. m. Output High Current (Sourcing): 00-07. TxD, RxC, m. m Output Low Current (Sinking): --DO-07. TxD, RxC, RTS. DTR. IRQ ' `OH -200 1 -400 - I /.A VOH = 2.4V IOL IOFF 1.6 - - 10 mA d v,, VOuT = = 0.4v Output Leakage Current (off state): IRQ Power Dissipation 5.0V PO - 7 10 20 10 mW/MHz vcc = 5.ov ; 1 Input Capacitance All except 02 CCLK GIN - 02 Output Capacitance PF PF PF vlN = ov f = 2 MHz T, 3: 25% COUT - 10 Notes: 1. All units are direct current (dc) except for capacitance. 2. Negative sign indicates outward current flow, positive indicates inward flow. 3. Tvolcal values are shown for Vrr = 5.OV and TA = 25C. |
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